Low Frequency CMUT with Vent Holes

ABSTRACT

A capacitive micromachined ultrasonic transducer (CMUT), which has a conductive structure that can vibrate over a cavity, has a number of vent holes that are formed in the bottom surface of the cavity. The vent holes eliminate the deflection of the CMUT membrane due to atmospheric pressure which, in turn, allows the CMUT to receive and transmit low frequency ultrasonic waves.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to CMUTS and, more particularly, to a lowfrequency CMUT with vent holes.

2. Description of the Related Art

A capacitive micromachined ultrasonic transducer (CMUT) is asemiconductor-based ultrasonic transducer that utilizes a change incapacitance to convert received ultrasonic waves into an electricalsignal, and to convert an alternating electrical signal into transmittedultrasonic waves.

FIGS. 1A-1B show views that illustrate an example of a prior-art CMUT100. FIG. 1A shows a plan view of CMUT 100, while FIG. 1B shows across-sectional view taken along line 1B-1B of FIG. 1A. As shown inFIGS. 1A-1B, CMUT 100 includes a conventionally-formed semiconductorsubstrate 110, and a post oxide structure 112 that touches the topsurface of semiconductor substrate 110. Post oxide structure 112, inturn, has substrate contact openings 114 that extend completely throughpost oxide structure 112 to expose semiconductor substrate 110.

As further shown in FIGS. 1A-1B, CMUT 100 includes a non-conductivestructure 116 that touches the top surface of semiconductor substrate110, and a conductive structure 120 that touches the top surface of postoxide structure 112 over non-conductive structure 116 to form avacuum-sealed cavity 122. In the present example, conductive structure120 includes a semiconductor structure 124 such as, for example, singlecrystal silicon, and an overlying metal structure 126, such as analuminum copper plate.

In addition, CMUT 100 includes substrate bond pads 130 that lie withinthe substrate contact openings 114 to make electrical connections tosemiconductor substrate 110, and a passivation layer 132 that touchesand lies over post oxide structure 112, conductive structure 120, andthe substrate bond pads 130. Passivation layer 132 has substrate bondpad openings 134 that expose the substrate bond pads 130, and aconductor opening 136 that exposes a region of conductive structure 120which functions as a bond pad. Further, CMUT 100 has an acousticdampening structure 140 that touches the bottom surface of semiconductorsubstrate 110.

In operation, a first bias voltage V1 is placed on semiconductorsubstrate 110, which functions as a first capacitor plate, and a secondbias voltage V2 is placed on conductive structure 120, which functionsas second capacitor plate. Thus, the voltage across the capacitor plateslies across vacuum-sealed cavity 122. When used as a receiver, anultrasonic wave causes conductive structure 120 to vibrate. Thevibration varies the capacitance across the first and second capacitorplates, thereby generating an electrical signal that varies as thecapacitance varies.

When used as a transmitter, an alternating electrical signal appliedacross the biased first and second capacitor plates causes conductivestructure 120 to vibrate which, in turn, transmits ultrasonic waves. Therate or frequency at which conductive structure 120 vibrates depends onthe volume of vacuum-sealed cavity 122, and the stiffness of conductivestructure 120.

In addition to transmitting ultrasonic waves outward, ultrasonic wavesare also transmitted backward towards the bottom surface ofsemiconductor substrate 110. These backward ultrasonic waves canresonate within semiconductor substrate 110 depending on the thicknessof semiconductor substrate 110 and the frequency of operation, and caninterfere with the quality of the resultant image. Acoustic dampeningstructure 140 absorbs and dampens the ultrasonic waves in semiconductorsubstrate 110.

FIGS. 2A-2B show views that illustrate an example of a prior-art CMUTarray 200. FIG. 2A shows a plan view of array 200, while FIG. 2B shows across-sectional view taken along line 2B-2B of FIG. 2A. As shown in theFIGS. 2A-2B example, CMUT array 200 includes three CMUTS 100 in a singlerow.

FIGS. 3A-3N show cross-sectional views that illustrate an example of aprior-art method of forming a CMUT. As shown in FIG. 3A, the methodutilizes a conventionally-formed single-crystal silicon wafer 310.Silicon wafer 310 has rows and columns of die-sized regions, and one ormore CMUTS can be simultaneously formed in each die-sized region. Forsimplicity, FIGS. 3A-3N illustrate the formation of a single CMUT.

As further shown in FIG. 3A, the method begins by forming a post oxidestructure 312 on the top surface of silicon wafer 310 using thewell-known local oxidation of silicon (LOCOS) process. The LOCOS processalso forms a backside oxide structure 314 at the same time. Followingthis, as shown in FIG. 3B, a cell oxide layer 316 is grown on theexposed regions of the top surface of silicon wafer 310.

After cell oxide layer 316 has been formed, as shown in FIG. 3C, asilicon-on-oxide (SOI) wafer 320 is fusion bonded to the top surface ofpost oxide structure 312 to form a cavity 322. SOI wafer 320 has ahandle wafer 324, an insulation layer 326 that touches handle wafer 324,and a single-crystal silicon substrate structure 328. Substratestructure 328, in turn, has a first surface that touches insulationlayer 326, and a second surface that touches post oxide structure 312.

Cavity 322, in turn, has a depth that is measured vertically from thetop surface of cell oxide layer 316 to the second surface of substratestructure 328. The thickness of cell oxide layer 316 defines theposition of the top surface of cell oxide layer 316. In addition, theheight of post oxide structure 312 over the top surface of silicon wafer310 defines the position of the second surface of substrate structure328.

The thickness of cell oxide layer 316 is relatively small compared tothe height of post oxide structure 312 over the top surface of siliconwafer 310. As a result, the depth of cavity 322 is substantially definedby the height of post oxide structure 312 over the top surface ofsilicon wafer 310. In addition, substrate structure 328 of SOI wafer 320is fusion bonded to the top surface of post oxide structure 312 ofsilicon wafer 310 in a vacuum to vacuum seal cavity 322.

After substrate structure 328 has been fusion bonded to post oxidestructure 312, as shown in FIG. 3D, handle wafer 324 is removed in aconventional manner, followed by the conventional removal of insulationlayer 326. Next, as shown in FIG. 3E, a patterned photoresist layer 330is formed on the first surface of substrate structure 328. Oncepatterned photoresist layer 330 has been formed, as shown in FIG. 3F,the exposed region of substrate structure 328 is etched to form a CMUTmembrane 332. Patterned photoresist layer 330 is then removed in aconventional manner.

As shown in FIG. 3G, after the removal of photoresist layer 330, apatterned photoresist layer 340 is formed on post oxide structure 312and CMUT membrane 332. Once patterned photoresist layer 340 has beenformed, as shown in FIG. 3H, the exposed regions of post oxide structure312 are etched until silicon wafer 310 has been exposed. Patternedphotoresist layer 340 is then removed in a conventional manner.

Following the removal of photoresist layer 340, as shown in FIG. 3I, ametal layer 342, such as a layer of aluminum copper, is deposited totouch silicon wafer 310, post oxide structure 312, and CMUT membrane332. After this, a patterned photoresist layer 350 is formed on metallayer 342.

Next, as shown in FIG. 3J, the exposed region of metal layer 342 isetched to form semiconductor bond pads 352 that extend through postoxide structure 312 to touch silicon wafer 310, and a metal plate 354that touches the top surface of CMUT membrane 332. Patterned photoresistlayer 350 is then removed in a conventional manner.

As shown in FIG. 3K, after patterned photoresist layer 350 has beenremoved, a passivation layer 356 is formed to touch post oxide structure312, CMUT membrane 332, the bond pads 352, and metal plate 354. Oncepassivation layer 356 has been formed, a patterned photoresist layer 360is formed on passivation layer 356.

After this, as shown in FIG. 3L, the exposed regions of passivationlayer 356 are etched to form openings that expose the semiconductor bondpads 352, and an opening, like opening 136 in FIG. 1A, that exposes abond pad region of metal plate 354. As shown in FIG. 3M, patternedphotoresist layer 360 is then removed in a conventional manner.

Next, the resulting structure is flipped over for processing, andbackside oxide structure 314 is removed in a conventional manner. Forexample, backside oxide structure 314 can be removed using chemicalmechanical polishing. Alternately, backside oxide structure 314 can beremoved using a single-sided wet etch, such as a SEZ etch.

Following the removal of backside oxide structure 314, an acousticdamping structure 362, such as a tungsten epoxy mixture, is depositedonto the bottom side of silicon wafer 310 to form, as shown in FIG. 3N,a CMUT 364. Silicon wafer 310 is then diced to form a number ofindividual die that each has one or more CMUTS 364.

In the present example, cavity 322 has a depth of approximately 0.2 μmand a diameter of approximately 36.0 μm. In addition, CMUT membrane 332,metal plate 354, and the overlying region of passivation layer 356vibrate at frequencies of approximately 10-20 MHz. These frequencies aresuitable for contact or near contact body imaging applications, likeecho cardiograms, but are not suitable for airborne ultrasoundapplications where, for example, the object to be detected, such as thehand motions of a person playing a game, is one or more meters away.

Instead, airborne ultrasound applications require much lowerfrequencies, such as 100-200 KHz. If CMUT 364 were scaled up in size tooperate at these lower frequencies, then CMUT 364 would require a largercell diameter (e.g. increasing from about 36 μm to about 1 mm-2 mm), athicker CMUT membrane 332 (e.g. increasing from 2 μm to 5 μm-40 μm), anda deeper cell cavity 322 (e.g. increasing from 0.2 μm to fpm-12 μm). Adeeper cell cavity is required to accommodate the atmospheric deflectionof CMUT membrane 332, which can be on the order of several microns. Forproper CMUT operation CMUT membrane 332 should not touch the bottomsurface of cavity 322, but rather be a fixed distance of one or moremicrons above the bottom surface of cavity 322.

Since the height of post oxide structure 312 substantially determinesthe depth of cavity 322, scaling up CMUT 364 requires that post oxidestructure 312 have a height above the top surface of silicon wafer 310of approximately fpm-12 μm, or a total thickness of 2 μm-24 μm. However,forming a post oxide structure with a thickness that exceedsapproximately 5 μm (or heights that exceed 2.5 μm) is difficult toaccomplish because the rate of oxide growth slows dramatically when thethickness of the post oxide structure approaches 5 μm.

As a result, it is difficult to scale up CMUT 364 to accommodate theselower frequencies. Thus, there is a need for an approach to forming lowfrequency CMUTS for airborne ultrasonic applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1B are views illustrating an example of a prior-art CMUT 100.FIG. 1A is a plan view of CMUT 100. FIG. 1B is a cross-sectional viewtaken along line 1B-1B of FIG. 1A.

FIGS. 2A-2B are views illustrating an example of a prior-art CMUT array200. FIG. 2A is a plan view of array 200. FIG. 2B is a cross-sectionalview taken along line 2B-2B of FIG. 2A.

FIGS. 3A-3N are cross-sectional views illustrating an example of aprior-art method of forming a CMUT.

FIGS. 4A-4B are views illustrating an example of a CMUT 400 inaccordance with the present invention. FIG. 4A is a plan view of CMUT400. FIG. 4B is a cross-sectional view taken along line 4B-4B of FIG.4A.

FIGS. 5A-5B are views illustrating an example of a CMUT array 500 inaccordance with the present invention. FIG. 5A is a plan view of array500. FIG. 5B is a cross-sectional view taken along line 5B-5B of FIG.5A.

FIGS. 6A-6S are cross-sectional views illustrating an example of amethod of forming a CMUT in accordance with the present invention.

FIGS. 7A-7B are views illustrating an example of a CMUT 700 inaccordance with an alternate embodiment of the present invention. FIG.7A is a plan view of CMUT 700. FIG. 7B is a cross-sectional view takenalong line 7B-7B of FIG. 7A.

FIGS. 8A-8B are views illustrating an example of a CMUT 800 inaccordance with an alternate embodiment of the present invention. FIG.8A is a plan view of CMUT 800. FIG. 8B is a cross-sectional view takenalong line 8B-8B of FIG. 8A.

FIGS. 9A-9B are views illustrating an example of a CMUT 900 inaccordance with an alternate embodiment of the present invention. FIG.9A is a plan view of CMUT 900. FIG. 9B is a cross-sectional view takenalong line 9B-9B of FIG. 9A.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 4A-4B show views that illustrate an example of a CMUT 400 inaccordance with the present invention. FIG. 4A shows a plan view of CMUT400, while FIG. 4B shows a cross-sectional view taken along line 4B-4Bof FIG. 4A. As described in greater detail below, CMUT 400 utilizes ventholes that allow CMUT 400 to receive and transmit low frequencyultrasonic waves.

As shown in FIGS. 4A-4B, CMUT 400 includes a semiconductor substrate 410that has a bottom surface 412 and a top surface 414, where the topsurface 414 lies in a plane 415. Semiconductor substrate 410, which isconductive, can be implemented with, for example, single-crystalsilicon.

In addition, semiconductor substrate 410 has a number of vent holes 416that extend down from the top surface 412 into semiconductor substrate410. Further, in the FIGS. 4A-4B example, semiconductor substrate 410has a backside opening 418 that extends up from the bottom surface 414into semiconductor substrate 410 to expose and open the vent holes 416.

In addition, CMUT 400 also includes a post oxide structure 420 thattouches the top surface 414 of semiconductor substrate 410 and lies bothabove and below plane 415. Further, post oxide structure 420, which isnon-conductive, laterally surrounds the vent holes 416. In the FIGS.4A-4B example, post oxide structure 420 also has substrate contactopenings 422 that extend completely through post oxide structure 420 toexpose semiconductor substrate 410.

As further shown in FIGS. 4A-4B, CMUT 400 includes a non-conductivestructure 424 that touches the top surface 414 of semiconductorsubstrate 410 and lines the vent holes 416 so that the vent holes remainopen. In addition, non-conductive structure 424, which can beimplemented with a layer of oxide, is laterally surrounded and touchedby post oxide structure 420. CMUT 400 also includes a non-conductivestructure 426 that touches the bottom surface 412 of semiconductorsubstrate 410 and lines backside opening 418 so that the vent holesremain open.

In addition, CMUT 400 includes a conductive structure 430 that touchesthe top surface of post oxide structure 420, and lies directlyvertically over the vent holes 416 to form a cavity 432 that liesvertically between the top surface of non-conductive structure 424 andconductive structure 430 over the top ends of the vent holes 416. In thepresent example, conductive structure 430 includes a semiconductorstructure 434 such as, for example, single crystal silicon, and anoverlying metal structure 436, such as an aluminum copper plate.

CMUT 400 further includes substrate bond pads 440 that lie within thesubstrate contact openings 422 to make electrical connections tosemiconductor substrate 410, and a passivation layer 442 that touchesand lies over post oxide structure 420, conductive structure 430, andthe substrate bond pads 440. Passivation layer 442, which isnon-conductive, has substrate bond pad openings 444 that expose thesubstrate bond pads 440, and a conductive opening 446 that exposes aregion of metal structure 436 that functions as a bond pad.

In operation, a first bias voltage V1 is placed on semiconductorsubstrate 410, which functions as a first capacitor plate, and a secondbias voltage V2 is placed on conductive structure 430, which functionsas second capacitor plate. Thus, the voltage across the capacitor plateslies vertically across cavity 432.

When used as a receiver, an ultrasonic wave causes conductive structure430 to vibrate. The vibration varies the capacitance across the firstand second capacitor plates, thereby generating an electrical signalthat varies as the capacitance varies. When used as a transmitter, analternating electrical signal applied across the biased first and secondcapacitor plates causes conductive structure 430 to vibrate which, inturn, transmits ultrasonic waves.

The primary advantage of CMUT 400 is that the vent holes 416 equilibratethe pressures on both sides of CMUT membrane 434, thereby eliminatingthe deflection due to atmospheric pressure. Without atmosphericdeflection, cavity 432 does not need to be as deep. As a result, it isstill possible to form cavity 432 using the LOCOS thermal oxidationmethod.

FIGS. 5A-5B show views that illustrate an example of a CMUT array 500 inaccordance with the present invention. FIG. 5A shows a plan view ofarray 500, while FIG. 5B shows a cross-sectional view taken along line5B-5B of FIG. 5A. As shown in the FIGS. 5A-5B example, CMUT array 500includes three CMUTS 400 in a single row.

FIGS. 6A-6S show cross-sectional views that illustrate an example of amethod of forming a CMUT in accordance with the present invention. Asshown in FIG. 6A, the method utilizes a conventionally-formedsingle-crystal silicon wafer 610 that has a bottom surface 612 and a topsurface 614, where the top surface 614 lies in a plane 615. In thepresent example, silicon wafer 610 has a low resistivity (e.g., 0.1Ω-cm). Silicon wafer 610 has rows and columns of die-sized regions, andone or more CMUTS can be simultaneously formed in each die-sized region.For simplicity, FIGS. 6A-6S illustrate the formation of a single CMUT.

The method begins by forming a patterned photoresist layer on the topsurface 614 of silicon wafer 610 in a conventional manner. After thepatterned photoresist layer has been formed, the top surface 614 ofsilicon wafer 610 is etched for a predefined time to form two or morefront side alignment marks.

If a wet etchant is used, the resulting structure is rinsed followingthe etch. After the rinse, the patterned photoresist layer isconventionally removed, such as with acetone. Following the removal ofthe patterned photoresist layer, the resulting structure is cleaned toremove organics, such as with a Piranha etch (e.g., using a solution of50H₂SO₄: 1 H₂O₂ @ 120° C. removes approximately 240 nm/minute).

Next, the method continues by forming a post oxide structure on the topsurface 614 of silicon wafer 610. The post oxide structure, which isnon-conductive, is formed using the well-known local oxidation ofsilicon (LOCOS) process. As illustrated in FIG. 6A, he LOCOS processbegins by forming a pad oxide layer 616 on the top surface 614 ofsilicon wafer 610, followed by the formation of a nitride layer 618 onthe top surface of pad oxide layer 616. Pad oxide layer 616 can have athickness of, for example, 250 Å, while nitride layer 618 can have athickness of, for example, 1500 Å.

After this, a patterned photoresist layer 620 is formed on nitride layer618 in a conventional manner.

Following the formation of patterned photoresist layer 620, as shown inFIG. 6B, the exposed region of nitride layer 618 is plasma etched toexpose a region of pad oxide layer 616. In addition, the etch leavesnitride regions 622. After this, patterned photoresist layer 620 isconventionally removed, such as with acetone. The resulting structure isthen cleaned to remove organics, such as with a Piranha etch, followedby a conventional pre-oxidization clean. (The cleaning andpre-oxidization cleans can be sequentially performed with the sameetchant.)

Next, as shown in FIG. 6C, the resulting structure is oxidized in asteam of, for example, 1100° C. for 18 hours, to grow the exposed regionof pad oxide layer 616 to form a post oxide structure 624. The growthalso leaves pad oxide regions 626 that lie below the nitride regions622, as well as forming a backside oxide structure 628. In the presentexample, post oxide structure 624 and bottom side oxide structure areboth grown to have a total thickness of, for example, 3 μm which, inturn, gives post oxide structure 624 a height above the top surface 614of silicon wafer 610 of 1.5 μm.

The top surface of post oxide structure 624 is substantially planar. Inaddition, the surface roughness of post oxide structure 624 must becontrolled to provide a good bonding surface. In the present example,the surface roughness must be less than 3 Å RMS. Further, laterallyadjacent sections of post oxide structure 624, which are substantiallydefined by the dimensions of the intermediate nitride region 622, arespaced apart by, for example, 0.5 mm. Following the formation of postoxide structure 624, the nitride regions 622 are removed in aconventional manner.

As shown in FIG. 6D, after the nitride regions 622 have been removed, apatterned photoresist layer 630 is formed on post oxide structure 624and the pad oxide regions 626 in a conventional manner. Next, theexposed regions of the pad oxide region 626 and the underlying regionsof silicon wafer 610 that lie between post oxide structure 624 are dryetched for a predefined time to form a number of vent holes 632.

For example, the well-known Bosch etch process can be used to form thevent holes 632 to have a diameter of, for example, 50 μm, andsubstantially vertical side walls that extend down to a depth of, forexample, 400 μm (to have an aspect ratio of 8:1). Although described ascircular in the present example, the vent holes 632 can have any shapeor combination of shapes, depending on the mask used to form patternedphotoresist layer 630.

As shown in FIG. 6E, after the vent holes 632 have been formed,patterned photoresist layer 630 is conventionally removed, such as withacetone. Following this, the resulting structure is cleaned to removeorganics, such as with a Piranha etch. The pad oxide regions 626 arethen removed without damaging the top surface of silicon wafer 610. Forexample, the pad oxide regions 626 can be removed using, for example, awet etchant that is highly or completely selective to silicon. Afterthis, the resulting structure is rinsed, and then subjected to aconventional pre-oxidization clean.

As shown in FIG. 6F, following the removal of the pad oxide regions 626,a cell oxide layer 634 is grown on the top surface 614 of silicon wafer610. Cell oxide layer 634, which has a thickness of, for example, 2500Å, also lines the side wall and bottom surfaces of the vent holes 632,which in the present example have diameters of 50 μm.

After cell oxide layer 634 has been formed, as shown in FIG. 6G, asilicon-on-oxide (SOI) wafer 640 is bonded to the top surface of postoxide structure 624 to form a cavity 642. In the present example, SOIwafer 640 is vacuum fusion bonded to post oxide structure 624 of siliconwafer 610 in a conventional manner so that cavity 642 has a vacuum,followed by an anneal to ensure reliable bonding strength. The annealcan be performed with a temperature in the range of 400° C. to 1050° C.In the present example, the anneal is performed at 1050° C. immediatelyafter the bonding for approximately four hours. Alternately, otherbonding approaches can also be used.

SOI wafer 640 has a handle wafer 644, an insulation layer 646 thattouches handle wafer 644, and a single-crystal silicon substratestructure 648. Substrate structure 648, in turn, has a firstsubstantially-planar surface that touches insulation layer 646, and asecond substantially-planar surface that touches post oxide structure624. In the present example, insulation layer 646 has a thickness of 1.1μm, and substrate structure 648 has a thickness of 2.2 μm.

As shown in FIG. 6H, after substrate structure 648 has been bonded topost oxide structure 624, handle wafer 644 is removed in a conventionalmanner. For example, handle wafer 644 can be removed by grinding handlewafer 644 down to a thickness of approximately 150 μm, and then wetetching the remainder away in a solution of KOH.

As shown in FIG. 6I, after handle wafer 644 has been removed, theresulting structure is flipped over for processing, and backside oxidestructure 628 is removed in a conventional manner. For example, backsideoxide structure 628 can be removed using chemical mechanical polishing.

Alternately, bottom side oxide structure 628 can be removed using asingle-sided wet etch, such as a SEZ etch by SEZ Austria GmbH,Draubodenweg 29, A-9500 Villach, Austria. Following the removal ofbackside oxide structure 628, a patterned photoresist layer 650 isformed on the bottom surface 612 of silicon wafer 610 in a conventionalmanner.

Once patterned photoresist layer 650 has been formed, as shown in FIG.6J, the exposed region of silicon wafer 610 is etched to form a backsideopening 652 that exposes and opens the vent holes 632 that are laterallysurrounded by post oxide structure 624, thereby breaking the vacuum incavity 642. For example, the well-known Bosch etch process can be usedto form backside opening 652 to have substantially vertical side wallsthat extend down to a depth of, for example, 350 μm or more.

As shown in FIG. 6K, after backside opening 652 has been formed,patterned photoresist layer 650 is conventionally removed, such as withacetone. Following the removal of patterned photoresist layer 650, theresulting structure is cleaned to remove organics, such as with aPiranha etch. In addition, a single-sided wet etch, such as a SEZ etch,can optionally follow to ensure that the vent holes 632 are open.

After this, a protective oxide layer 654 is grown on the bottom surface612 of silicon wafer 610 to line backside opening 652 during an annealin a conventional manner. The anneal can be performed with a temperaturein the range of 400° C. to 1050° C. In the present example, the annealis performed at 1050° C. for approximately four hours. Protective oxidelayer 654 can be grown to have a thickness of, for example, 2500 Å. (Thegrowth of protective oxide layer 654 also increases the thickness ofcell oxide layer 634 by a similar amount.)

After protective oxide layer 654 has been formed, as shown in FIG. 6L,the resulting structure is flipped and insulation layer 646 is removedin a conventional manner. For example, insulation layer 646 can beremoved using chemical mechanical polishing. Alternately, insulationlayer 646 can be removed using a single-sided wet etch, such as a SEZetch. Following the removal of insulation layer 646, a patternedphotoresist layer 660 is formed on the first surface of substratestructure 648 in a conventional manner.

Once patterned photoresist layer 660 has been formed, as shown in FIG.6M, the exposed regions of substrate structure 648 are etched to form aCMUT membrane 662 that lies directly vertically over the vent holes 632.In addition, the etch also exposes the alignment marks. If a wet etchantis used, the resulting structure is rinsed following the etch. After therinse, patterned photoresist layer 660 is conventionally removed, suchas with acetone. Following the removal of patterned photoresist layer660, the resulting structure is cleaned to remove organics, such as witha Piranha etch.

As shown in FIG. 6N, after the cleaning following the removal ofpatterned photoresist layer 660, a patterned photoresist layer 670 isformed on post oxide structure 624 and CMUT membrane 662 in aconventional manner. Once patterned photoresist layer 670 has beenformed, the exposed regions of post oxide structure 624 are etched toform openings 672 that expose silicon wafer 610.

In the present example, the openings 672 each has a diameter of 50 μm.If a wet etchant is used, the resulting structure is rinsed followingthe etch. After the rinse, patterned photoresist layer 670 isconventionally removed, such as with acetone. Following the removal ofpatterned photoresist layer 670, the resulting structure is cleaned toremove organics, such as with a Piranha etch.

After cleaning following the removal of patterned photoresist layer 670,as shown in FIG. 6O, a metal layer 674, such as a layer of aluminumcopper, is deposited to touch silicon wafer 610, post oxide structure624, and CMUT membrane 662. In the present example, metal layer 674 isformed to have a thickness of 1 μm. Next, a patterned photoresist layer680 is formed on metal layer 674 in a conventional manner.

As shown in FIG. 6P, after patterned photoresist layer 680 has beenformed, the exposed region of metal layer 674 is wet etched to formsemiconductor bond pads 682 that each extends through post oxidestructure 624 to touch silicon wafer 610, and a metal plate 684 thattouches the top surface of CMUT membrane 662. Following the etch, theresulting structure is rinsed. After the rinse, patterned photoresistlayer 680 is conventionally removed, such as with acetone.

After the removal of patterned photoresist layer 680, as shown in FIG.6Q, a passivation layer 686, such as a layer of plasma oxideapproximately 0.6 μm thick and an overlying layer of plasma nitrideapproximately 0.6 μm thick, is deposited on post oxide structure 624,CMUT membrane 662, the bond pad structures 682, and metal plate 684.Next, a patterned photoresist layer 690 is formed on passivation layer686 in a conventional manner.

As shown in FIG. 6R, after patterned photoresist layer 690 has beenformed, the exposed regions of passivation layer 686 are wet etched toform openings that expose the bond pad structures 682, and an opening,like opening 446 shown in FIG. 4A, that exposes a bond pad region onmetal plate 684. Following the etch, the resulting structure is rinsed.

After the rinse, as shown in FIG. 6S, patterned photoresist layer 690 isconventionally removed, such as with acetone. After the removal ofpatterned photoresist layer 690, the resulting structure is alloyed at,for example, 400° C. in a ambient of N₂+H₂ to form a CMUT 692.

One of the advantages of CMUT 692 is that the vent holes 632 allow alow-frequency CMUT to be formed in a process that includes aconventional LOCOS process to form post oxide structure 624. Inaddition, the vent holes 632 are exposed to the atmosphere and, thus,experience no degradation due to altitude. (The accuracy of large vacuumsealed cavities degrades with altitude.)

FIGS. 7A-7B show views that illustrate an example of a CMUT 700 inaccordance with an alternate embodiment of the present invention. FIG.7A shows a plan view of CMUT 700. FIG. 7B shows a cross-sectional viewtaken along line 7B-7B of FIG. 7A. CMUT 700 is similar to CMUT 400 and,as a result, utilizes the same reference numerals to designate theelements which are common to both CMUTS.

As shown in FIGS. 7A-7B, CMUT 700 differs from CMUT 400 in that CMUT 700omits the steps required to form backside opening 418 and non-conductivestructure 426 (but includes the second four hour anneal beforeinsulation layer 646 is removed). As a result, each vent hole 416 has abottom surface that lies above and vertically spaced apart from thebottom surface 412 of semiconductor substrate 410. Thus, a region ofsemiconductor substrate 410 touches and lies directly vertically betweenthe bottom surface of each vent hole 416 and the bottom surface 412 ofsemiconductor substrate 410.

In addition, CMUT 700 includes a backside oxide structure 710 thattouches the bottom side 412 of semiconductor substrate 410. Backsideoxide structure 710, which can optionally be removed in the same mannerthat backside oxide structure 628 is removed, is formed automatically atthe same time that post oxide structure 420 is formed.

Further, conductive structure 430 can be vacuum fusion bonded at lessthan a complete vacuum, for example, 75% atmospheric pressure. Bondingat a partial atmospheric pressure reduces the deflection of CMUTmembrane 434, and enables the continued use of the LOCOS thermaloxidation process to form a CMUT cell. CMUT 700 operates the same asCMUT 400.

One advantage of CMUT 700 is that the vent holes 416 substantiallyincrease the effective volume of cavity 432. Increasing the effectivevolume without increasing the distance between the two capacitor plateshas the positive effect of greatly reducing squeeze film damping, whichis the loss of accuracy due to the compression of air within the cavity.The volume of the vent holes 416 could increase the effective cavityvolume by a factor of 100×. In addition to increased volume, the effectof squeeze film dampening is also a function of the vent hole depth, thevent hole shape, and the vent hole location.

Another of the advantages of CMUT 700 is that since the vent holes 416remain closed and under a partial vacuum, no contaminants or foreignobjects can become undesirably lodged in the vent holes 416. Further,the costs associated with the backside processing (the mask and etch)are also eliminated.

FIGS. 8A-8B show views that illustrate an example of a CMUT 800 inaccordance with an alternate embodiment of the present invention. FIG.8A shows a plan view of CMUT 800. FIG. 8B shows a cross-sectional viewtaken along line 8B-8B of FIG. 8A. CMUT 800 is similar to CMUT 700 and,as a result, utilizes the same reference numerals to designate theelements which are common to both CMUTS.

As shown in FIGS. 8A-8B, CMUT 800 differs from CMUT 700 in that CMUT 800omits the substrate contact openings 422 and the substrate bond pads 440that lie within the substrate contact openings 422. As a result, noconductive structure extends through post oxide structure 420 in theFIGS. 8A-8B example.

In addition, CMUT 800 includes a backside bond pad structure 810 thattouches the bottom side 412 of semiconductor substrate 410. Backsidebond pad structure 810 can be formed by removing backside oxidestructure 710 of CMUT 800 in the same manner that backside oxidestructure 628 is removed. Following this, a metal layer, such as 100 Åof titanium and 1 μm of aluminum copper, is deposited onto the bottomsurface 412 of semiconductor substrate 410. The metal layer can also beimplemented with other common back side metallization stacks, such asTiNiAg, TiNiAu, CRAu, or TiAu. CMUT 800 otherwise operates the same asCMUT 700. One of the advantages of CMUT 800, in addition to theadvantages of CMUT 700, is that CMUT 800 eliminates the costs associatedwith forming the substrate contact openings 422.

FIGS. 9A-9B show views that illustrate an example of a CMUT 900 inaccordance with an alternate embodiment of the present invention. FIG.9A shows a plan view of CMUT 900. FIG. 9B shows a cross-sectional viewtaken along line 9B-9B of FIG. 9A. CMUT 900 is similar to CMUT 800 and,as a result, utilizes the same reference numerals to designate theelements which are common to both CMUTS.

As shown in FIGS. 9A-9B, CMUT 900 differs from CMUT 800 in that CMUT 900omits the vents holes 416, but instead utilizes peripheral vent holes910 in conductive structure 430 and passivation layer 442 to vent cavity432. In addition, CMUT 900 utilizes a non-conductive structure 912,which only touches the top surface 414 of semiconductor substrate 410,in lieu of non-conductive structure 424.

The vent holes 910 can be formed prior to the formation of passivationlayer 686 by forming a patterned photoresist layer on metal plate 684,followed by an etch through metal plate 684 and CMUT membrane 662. Thepatterned photoresist layer is then removed, followed by the formationof passivation layer 686.

During the formation of passivation layer 686, small amounts ofpassivation layer 686 will be deposited on the top surface ofnon-conductive structure 912. However, because the vent holes 910 areperipheral, the small amounts of passivation layer 686 on the topsurface of non-conductive structure 912 do not prevent CMUT 900 fromvibrating the same as CMUT 800, except that air flows through theperipheral vent holes 910 as conductive structure 662 vibrates.

It should be understood that the above descriptions are examples of thepresent invention, and that various alternatives of the inventiondescribed herein may be employed in practicing the invention. Thus, itis intended that the following claims define the scope of the inventionand that structures and methods within the scope of these claims andtheir equivalents be covered thereby.

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 15. (canceled)16. A semiconductor transducer comprising: a substrate having a bottomsurface and a top surface and being conductive, the top surface lying ina plane; a post structure that touches the top surface of the substrate,the post structure having a top surface and being non-conductive, aportion of the post structure lying below the plane and a portion of thepost structure lying above the plane; a non-conductive structure thattouches the top surface of the substrate, the post structure laterallysurrounding the non-conductive structure; and a conductive structurethat touches the top surface of the post structure and lies directlyvertically over the non-conductive structure to form a cavity, theconductive structure having a plurality of vent holes that extendcompletely through the conductive structure to expose the cavity. 17.(canceled)
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 21. Thesemiconductor transducer of claim 16 wherein the post structurelaterally surrounds and touches the non-conductive structure.
 22. Thesemiconductor transducer of claim 16 wherein the conductive structureincludes: a single-crystal silicon structure; and a metal plate thattouches the single-crystal silicon structure.
 23. The semiconductortransducer of claim 16 and further comprising a metal bond pad structurethat touches the bottom surface of the substrate.
 24. The semiconductortransducer of claim 16 wherein no conductive structure extends throughthe post structure.